1. Technical Field
The disclosed embodiments relate generally to frequency dividers, including frequency dividers operable in wireless communication systems.
2. Background Information
For some applications, such as wireless communication systems it is useful to include a frequency divider circuit. In one example, a frequency divider receives an oscillatory input signal, frequency divides the input signal, and generates a divided-down oscillatory output signal. The frequency division is characterized as frequency division by an integer. Within a wireless communication system, frequency dividers see frequent use as part of a radio transceiver (transmitter/receiver). In one example within a radio transceiver, a frequency divider may be used to receive an oscillatory signal from a Local Oscillator (LO), divide-down the oscillatory signal in frequency, and generate two lower frequency output signals: a differential in-phase (I) output signal and a differential quadrature (Q) output signal. The frequencies of output signals I and Q may, for example, be half the frequency of the input signal. The Q output signal is of the same frequency as the I output signal, but shifted ninety degrees in phase with respect to the I output signal. As such, differential output signals I and Q are said to be in phase quadrature. The set of divided-down output signals may, for example, be supplied to a mixer in a receive chain of the radio transceiver. This is but one application of a frequency divider within a wireless communication system. Frequency dividers may also see use within a Phase-Locked Loop within a local oscillator, or may also be used to frequency divide signals in other places within the wireless communication system circuitry.
FIG. 1 (Prior Art) is a diagram of a type of frequency divider circuit 1. Frequency divider 1 includes two conventional Injection-locked Frequency Dividers (ILFD) 2 and 3. Frequency divider 1 receives a differential input signal LO involving signal LO+ on conductor 4 and signal LO− on conductor 5. Divider 1 generates two differential output signals, I and Q. Differential output signal I involves signal I+ on conductor 6 and signal I− on conductor 7. Differential output signal Q involves signal Q+ on conductor 8 and signal Q− on conductor 9. Both ILFD 2 and 3 are a type of oscillatory circuit. For example, if an input signal of constant voltage is applied to ILFD 2, it will simply oscillate at its own natural frequency. However, if an oscillatory input signal of sufficient amplitude that falls within an acceptable frequency window is applied to ILFD 2, it will “lock” to the frequency of the oscillatory input signal and oscillate at half of the frequency of the oscillatory input signal. Thus, frequency divider 2 is operable to frequency divide input signal LO by integer two and generate output signals in phase quadrature. Although, the circuit of FIG. 1 operates satisfactorily in some applications, it has limitations. Due to the use of inductive loads, the physical size of a conventional ILFD is undesirably large. In addition, the inductors act as both a transmitter and receiver of Electro-Magnetic Interference (EMI) within the context of a larger circuit. Thus, the inductors inhibit the performance of other circuit elements and the performance of frequency divider 1 is inhibited by other circuit elements. In addition, the range of input frequencies to which the conventional ILFD will reliably “lock”, and hence divide, is limited to a relatively small percentage of the center tuned input frequency for typical input signal amplitudes. A broader range can be achieved by increasing the input signal amplitude or reducing the inductor quality factor but this approach consumes more power. An elaborate digitally controlled capacitor tuning bank may be employed to broaden the effective range of the ILFD to a practical range of 30-40% of the center tuned input frequency, but this approach is undesirably complex and consumes die area.
FIG. 2 (Prior Art) is a diagram of another type of frequency divider circuit 10. Frequency divider 10 includes two cross-coupled Common Mode Logic (CML) circuits 11 and 12. Frequency divider 10 receives a differential input signal LO involving signal LO+ on conductor 13 and signal LO− on conductor 14. Divider 10 generates two pairs of differential output signals, I and Q. Differential output signal I involves signal I+ on conductor 15 and signal I− on conductor 16. Differential output signal Q involves signal Q+ on conductor 17 and signal Q− on conductor 18. CML circuit 11 includes transistors TR1-TR6. LO− is supplied to transistor TR3 and LO+ is supplied to transistor TR4. Transistors TR1 and TR2 sense the state of CML circuit 12 and transfer this state to the load resistors of CML circuit 11 when TR3 is clocked high by LO−. When TR3 is clocked low by LO− and TR4 is clocked high by LO+, transistors TR5 and TR6 latch the state of the resistors of CML 11 during this phase of the clock cycle. In this manner, output signals I+ and I− oscillate at half the frequency of LO. Similarly, output signals Q+ and Q− oscillate at half the frequency of LO. However, since CML 12 receives LO+ and LO− in opposite polarity compared to CML 11, the differential output pair (Q+, Q−) and the differential output pair (I+, I−) are in phase quadrature. A limitation of frequency divider 10 is that the output voltage swing of the divider is not rail to rail. In practice, the low output swing of frequency divider 10 may only reach a few hundred millivolts above ground (VSS). As a result of this reduced range, phase noise performance of the divider is low relative to other solutions. In addition, a rail to rail converter must be employed to interface frequency divider 10 with inverter type passive mixer buffer stages. Rail to rail converters consume a large amount of power in the frequency range of hundreds of megahertz to a few gigahertz.
Another type of frequency divider is a dynamic logic divider utilizing transistor-based inverters. Unfortunately, the inverters require relatively high voltage supply rails to divide. In practice, a supply voltage greater than two threshold voltages plus two drain-source saturation voltages is needed for the inverter to have enough gain to operate reliably. A second disadvantage is that a dynamic logic divider requires a rail to rail input signal to divide. In practical circuit design, the input signal from a local oscillator is communicated over a signal line that often exceeds one millimeter in length. Over this distance, power losses along the line tend to attenuate the amplitude of the oscillatory signal. To overcome these losses and deliver a rail to rail signal to the divider, a more powerful signal must be transmitted by the local oscillator, resulting in undesirable levels of power consumption. In applications such as in a radio transceiver of a battery powered cellular telephone, it may be desired to operate a frequency divider that receives attenuated oscillatory input signals and generates low phase noise, rail to rail I and Q signals with minimal power consumption.